Microelectronic device for storing information with switchable ohmic resistance

ABSTRACT

A microelectronic device is designed such that it includes a region between electrodes having a switchable ohmic resistance wherein the region is made of a substance comprising components A x , B y , and oxygen O z . The ohmic resistance in the region is reversibly switchable between different states by applying different voltage pulses. The different voltage pulses lead to the respective different states. An appropriate amount of dopant(s) in the substance improves the switching, whereby the microelectronic device becomes controllable and reliable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic and microelectronic devices.In particular, the present invention relates to a plurality of materialsshowing a switching phenomenon and a built-in memory by the aid of whicha new principle of storing and reading information in memory cells ofsemiconductor chips and a plurality of fundamental improvements onelectronic or microelectronic devices can be achieved.

2. Description and Disadvantages of Prior Art

Although the present invention is applicable in a broad variety ofmicroelectronic or electronic applications it will be described with thefocus put on an application to memory cells as RAM (Random AccessMemory), for example.

The need to remain cost and performance competitive in the production ofsemiconductor devices has caused continually increasing device densityin integrated circuits. To facilitate the increase in device density,new technologies are constantly needed to allow the feature size ofthese semiconductor devices to be reduced.

Conventional DRAM cells, whereby DRAM stand for Dynamic Random AccessMemory, consist of a transistor and a capacitor mostly made from Silicondioxide (SiO2). They need the transistor to control the inflow andoutflow of charge stored in the capacitor as the physical quantityexploitable for storing information. Said transistor also decouples thecapacitors from each other. Such DRAM cells have the disadvantage, thatinformation stored therein is volatile and as such can principally belost on each power supply failure. Further, the time needed to refreshthe information contained in DRAM cells delimits the read and writeperformance of such cells. Finally, the structure of such a DRAM cell isquite complex due to the required transistor.

Thus, a change in computer RAM technology beyond conventional DRAMtechnology would be desirable.

The use of ferroelectric non-volatile RAM (NVRAM) cells would already bea great step forward as information would not be lost on any powerfailure although the structure of the memory cell would remain complex,too. In such ferroelectric RAMs the polarization of the bit storinglayer is exploited instead of a capacitor's capacity in DRAM cells fordefining two different states which can be associated with two differentlogical values. A long term repetitive switching between two differentstates of remanent polarization, however, fatigues the ferroelectricproperties of the material, as e.g. lead zirconium lot titanate (PZT).

In ‘Physics Today’ July 1998, page 24 a further high permittivitymaterial and a respective semiconductor fabricating technology isproposed which allows the computer industry to use the equipment of itsconventional DRAM manufacturing plants without having to perform basicretooling. It is the so-called high permittivity DRAM technology.

Herein, the charge of a capacitor can be used to store information as itis done in conventional DRAM technology as the polarization of a highpermittivity layer depends linearly on the applied voltage, as requiredfor charging the DRAM capacitors. A high permittivity material as e.g.barium strontium titanate (BST) having a permittivity er about 500instead of er about 4 for silicon dioxide would allow to reduce thespace needed for the capacitor as its capacitance is proportional to itsarea and the magnitude of its permittivity value. This in turn wouldallow higher integration levels compared to conventional silicon oxidematerials used in DRAM cells as the capacitor's area consumption islarge as compared to that of the coupled transistor.

But, nevertheless, as a disadvantage remains that the leakage current isstill significant.

Thus, refreshing is a must.

Investigations in the sixties at oxide diodes and thin oxide filmsrevealed several phenomena. For example, J. F. Gibbons and W. E. Beadlereports in their article “Switching properties of thin NiO films”,Solid-State Electronics, Pergamon Press 1964, Vol. 7, pp. 785-797, abouta two-terminal solid-state switch made from a thin film of nickel oxide.After about 100-1000 switching cycles, the device could not be switchedout of an ON condition with normal switching signal amplitudes. Othertests on oxide diodes were performed whereby switching was induced byapplying high voltages. These diodes broke down after a few cycles andbecame unusable. T. W. Hickmott reports in Applied Physics Letters, Vol.6, No. 6, on page 106 and in the Journal of Vacuum Science andTechnology, Vol. 6, No. 5 on page 828 about bistable switching inNiobium oxide diodes. He noticed that the metal electrode plays animportant role. To sum up, the tested devices and materials showed thatthey were either difficult to control or unreliable.

In U.S. Pat. No. 4,931,763 a memory switch is described that bases onmetal oxide thin films. The memory switch is irreversible and thereforeonly switches once. It can be used as connection element in circuits andarrays but not for storing of changing information.

Finally, with increasing integration near and beyond the 1 Gbit chip dueto smaller capacitor size the area consumption of the transistor of amemory cell is not negligible anymore. Thus, a great step forward toUltra Large Scale Integration (ULSI) would be to simplify the structureof a memory cell as much as possible.

OBJECTS OF THE INVENTION

Therefore, an object of the present invention is to provide a robustsimply structured, reliable and non-volatile memory cell.

It is another object of the present invention to provide a new simplermethod for stable storage of information into such a memory cell and areproducible erasing and reading from it.

It is another object of the present invention to provide a simplystructured and non-volatile memory cell which is able to store more thanonly two distinct values, i.e., which is usable for multilevel storage.

SUMMARY AND ADVANTAGES OF THE INVENTION

These objects of the invention are achieved by the features stated inthe following description and claims.

The basic discovery underlying the present invention concerns aplurality of doped oxide substances including perovskites and relatedcompounds, i.e. materials, for use in microelectronic devices and inelectronic circuits and particularly for use in semiconductor chipswhich combine both, a switching phenomenon in resistance and a built-inmemory.

A feature of the present invention includes a microelectronic devicedesign such that it comprises a region between electrodes having aswitchable ohmic resistance wherein the region is made of a substancecomprising components Ax, By, and oxygen Oz. The ohmic resistance in theregion is reversibly switchable between different states by applyingdifferent voltage pulses. The different voltage pulses lead to therespective different states. An appropriate amount of dopant(s) in thesubstance improves the switching, whereby the microelectronic devicebecomes controllable and reliable.

In general and coinciding with the wording of the claims substances aremeant comprising components A x, B y, and oxygen Oz, in which substancesaid component A is a member of Alkaline metals (group IA in theperiodic system of elements), or Alkaline Earth metals (group IIA), orRare Earth elements, or Scandium, or Yttrium, said component B is atransition metal being member of one of the groups IB to VIII, or amember of one of the groups IIIA, IVA, VA and the substance has acrystalline structure.

Various other objects, features, and attendant advantages of the presentinvention will become more fully appreciated as the same becomes betterunderstood when considered in conjunction with the accompanyingdrawings, in which like reference characters designate the same orsimilar parts throughout the several views.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the shape of the figures of the accompanying drawings.

FIG. 1 is a schematic drawing of a perovskite oxide capacitor-likestructure of a microelectronic device usable as memory cell inaccordance with the present invention.

FIGS. 2A to 2C show current-voltage characteristics of a 300 nm thick Crdoped oxide capacitor-like structure in accordance with the presentinvention.

FIGS. 3A to 3C show the principles of operation of the capacitor-likestructure analyzed in FIGS. 2A to 2C as a memory device in accordancewith the present invention.

FIGS. 4A to 4C show the operation of a further microelectronic device asa multilevel memory device in accordance with the present invention.

FIGS. 5A to 5H show results of measurements over an extended time periodin accordance with the present invention.

FIG. 6 shows a schematic circuit diagram representing the arrangement ofa 4-bit-memory circuit in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Generally, an elementary cell of the corresponding lattice structurecomprises a cell center molecule which is surrounded by a plurality ofoxygen-molecules each having in turn a center molecule. Both types ofsaid center locations can principally be taken by either of thecomponent A, or B, respectively. In other words, there are a pluralityof substances, i.e., where chemically appropriate, in which A and B canchange their locations. In view of the large plurality of the differentusable substances this understanding of the basic formula given aboveshould be stressed in order to assure the intended scope and to conserveclarity and conciseness of the appended claims, a concurrently.

Said substances comprise some specific range of amount of a dopant ofone of or a combination of Chromium, Vanadium, or Manganese, or furthertransition metals.

In particular, any substance comprising components A x, B y, and oxygenOz, in which substance said component A is a member of Alkaline metals(group IA), or Alkaline Earth metals (group IIA), or Rare Earthelements, or Scandium, or Yttrium, and said component B is a transitionmetal being member of one of the groups IB to VII, or a member of one ofthe groups IIIA, IVA, VA are substances which are able to solve theproblem underlying to the present invention, when doped with a dopant ofone of or a combination of transition metals, in particular but notexclusively with Chromium, Vanadium, or Manganese, the total dopantamount in atomic percentage being larger than 0% and smaller than 5%,and preferably about 0.2% when (BaSr)TiO₃ is doped with Chromium only.

Other preferred amounts of dopants are specific for each dopant elementused and substance to be doped.

Having found the appropriate amount of dopant(s), a stable switchingbehavior required to operate a microelectronic device, such as a memorycell, can be provided. Fast write, read and erase processes, similar totime scales that are reached with conventional dynamic memories, areachievable.

Some additional specific requirements should be met by the combinationof indices x, y, z in order to find the substances adapted to thepresent concept. Each of the following items define a subclass ofsubstances which show the desired switching effect:

The combinations of indices x, y and z being defined by

x=n+2, y=n+1, z=3n+4, with n=0, 1, 2, 3 reveal the so-called RuddlesdenPopper phases like e.g., Sr₂RuO₄ (xyz-index sequence 214) or Sr₃Ru₂O₇(xyz=327) and others.

The combinations of indices as defined above with n=0 contain amongothers a separate class of substances which adopt a spinell structure asit is e.g., Mg2TiO4 (214), Cr₂MgO₄, Al₂MgO₄ with A and B positionsreversed, i.e. the B cations originally indexed by y are located on theposition indexed by x and the A cations on the position indexed by y, orsubstances with x and y indexing B cations only (B₂BO₄), examples areFe₂CoO₄, Fe₂FeO₄ (Fe₃O₄).

The combinations of indices x, y and z being defined by

x=n+1, y=n+1, z=3n+5, with n=1, 2, 3, 4 reveal a separate class ofsubstances which partly provide substances having an oxygenintercalation.

The combinations of indices x, y and z being defined by either of:

x=1, y=1, z=1,

and one of the indices x or y being 0, reveal exemplary substances likeBeO, MgO, BaO, CaO, . . . NiO, MnO, CoO, CuO, ZnO, or

x=n, y=n, z=n+1 with n=1 or 2

and one of the indices x or y being 0, for n=1, reveal substances likeTiO2, VO2, MnO2, GeO₂, CeO₂, PrO₂, SnO₂,

for n=2, reveal substances like Al₂O₃, Ce₂O₃, Nd₂O₃, Ti₂O₃, Sc₂O₃, La₂O₃or

x=n, y=n, z=2n+1 with n=2

and one of the indices x or y being 0, reveal exemplary substances likeNb₂O₅, Ta₂O₅ and others.

The combinations of indices x, y and z being defined by

x=n, y=n, z=3n, with n=1, or 2, or 3 reveal a separate class ofsubstances for n=1 the so-called perovskites, like SrTiO₃, BaTiO₃,KNbO₃, LiNbO₃, and others,

for n=2 Sr₂FeMoO₆ and similar substances are provided having a (226)index sequence.

The combinations of indices x, y and z being defined by

x=n+1, y=n, z=4n+1, with n=1, or 2 reveal a separate class ofsubstances.

For n=1 substances having an index sequence (215) like Al₂TiO₅, Y₂MOO₅and others are provided, and

SrBi₂Ta₂O₉ and similars are provided for n=2.

Each of the classes mentioned above can be modified by varying thecomposition of the substance in order to achieve that at least one ofsaid components Ax or By, respectively, is comprised of a combination ofelements out of one group or out of several of the corresponding groupsof A, and B, respectively.

A further modification is provided by providing a superlattice made by acombination of structural unit cells and/or sub-unit cells as it ispublished in ‘E. Kaldis et al. (eds.), High-Tc Superconductivity 1996:Ten Years After Discovery, pp. 95-108’, having each a different n, andin which structural unit cells and/or sub-unit cells are each a memberof a corresponding homologous series obtained by oxygen intercalation. Afurther modification is provided by providing a superlattice made by acombination of structural unit cells and/or sub-unit cells of theRuddlesden-Popper type structures having each a different n, and inwhich said structural unit cells and/or sub-unit cells are each a memberof a corresponding homologous series. In said lattice modificationslattice structures are formed in which single or multiple transitionmetal oxygen octahedra layers are separated by one or more block layersconsisting of component A and oxygen.

One preferred member of that plurality of substances isBa_(x)Sr_(1-x)TiO₃ with 0<=x<=0.7 and having a dopant amount of Chromiumin atomic percentage of between 0% and 5%, preferably between 0 and 1%,even more preferably about 0.2%.

Others members of that plurality are materials according toBa_(x)Sr_(1-x),TiO₃ with 0<=x<=0.7 and having a dopant of Vanadium inatomic percentage of between 0% and 5%.

Manganese is a preferred dopant, too, particularly in composition withChromium or Vanadium.

Further members of that plurality are perovskite related compounds withother transition metal cations such as Nb. Further dopants can betransition metal elements and combinations thereof, i.e., elementshaving their valence electron(s) on the d-orbital, i.e., 3 d, 4 d, or 5d-orbital.

When such a material is used for example as a dielectric layer in acapacitor-like structure to form the microelectronic device, it staysswitched in either a high or a low conductivity state depending on avoltage pulse being applied to it until it is switched into the otherstate by applying a new voltage pulse. Thus, said capacitor-likestructure having such a complex dielectric material has a resistancewhich can be varied by applying short voltage or, alternatively, shortcurrent pulses to the embedding electrodes.

As the most decisive electrical property of such a microelectronicdevice is the change in resistance depending on a defined, appliedvoltage pulse between the two terminals of the microelectronic device,whereby said capacitor-like structure can be regarded as a ‘switchableresistor’. Said switching behavior is known to be effectuated by avoltage or current driven hysteresis behavior.

Due to said property it is possible to store digital information bydifferent values of it resistance, i.e., by associating a highresistance state with a logic ‘0’ and a low resistance state with alogic ‘1’. The actual state and thus the stored information can be readout by a current readout or measuring the leakage current as it isrelatively large with low resistance of the dielectric layer and viceversa. Thus, the leakage current which impedes the performance of priorart DRAM technology can be usefully taken for reading the stored value.According to the invention neither the static charge of a capacitor northe polarization of any ferroelectric material is needed to be used forstoring information but, instead, its resistance.

Thus, a simple way to store information can be followed by realizing theabove mentioned concept.

The material usable in connection with the present invention when usedfor e.g. RAM cells has the advantage, in relation to prior art memorycells, that new cells can be constructed just comprising a singlecapacitor-like structure device with only one pair of electrodeterminals for operating it, i.e. to read from, to write into or to erasewithout a transistor arrangement being necessarily coupled with acapacitor used in prior art to perform the operating functions of aprior art DRAM cell. One terminal of such a cell is connected to groundand the other is used for writing, erasing or just reading.

Thus, RAM cells can be constructed to use considerably less space on achip and considerable less manufacturing steps.

Further, the usable material has a remarkable high retention time of atleast several months with no power connected and can thus be used as anon-volatile memory. Thus a double advantage can be achieved: first, thefull time is available for the read and write processes because therefresh cycles and therefore the refresh circuitry are not requiredanymore and, secondly, a data storage security is increased as a loss ofpower supply does not imply a loss of stored data.

Basically, the memory cell can be operated in either a voltagecontrolled or in a current Fit controlled regime, i.e. information canbe stored by applying voltage pulses or by applying current pulses. Inboth cases the information can be read by sensing voltage or current.For purposes of improved clarity of this disclosure, however, only thevoltage regime is described in the detailed description down below.

Finally, for example in the voltage controlled mode the current flowingwhen reading a ‘1’ compared to that one when reading a ‘0’ value isabout 20 times larger due to the difference in resistance. This featurecan advantageously be used for storing more than only one bit in thesame cell. Thus, a plurality of two, three, or more bits can be storedor removed by applying different voltage pulses, single pulses orsequences thereof having different shape, level, or duration or beingdifferent in number to write and erase. A sufficiently large distancebetween the different levels can hereby be maintained.

With general reference to the figures and with special reference to FIG.1 the essential structure of a microelectronic device 10 having acapacitor-like structure is described in more detail. Such amicroelectronic device 10 is useable as a memory cell.

The microelectronic device 10 comprising an oxide base electrode 12 madefrom SrRuO₃ and a region 14 with an oxide insulator layer made from(BaSr)TiO₃ slightly doped with Chromium (Cr) for the insulating materialand a metallic Gold (Au) top electrode 16 on a SrTiO₃ substrate 18 wasfabricated with pulsed laser deposition. The microelectronic device 10has a thin film capacitor-like structure.

One terminal 20 is connected to said top electrode 16, the otherterminal 22 is connected to said base electrode 12.

In an arrangement setup for testing the basic switching behavior andfurther physical properties of the microelectronic device 10 theinsulator layer thickness was 300 nanometers.

The insulator layer of the region 14 was doped with Chromium (Cr) at anamount of

The leakage current was measured as it is depicted in the drawing as afunction of the bias voltage generated by a DC voltage source 24 betweensaid terminals 20, 22.

With respect to FIGS. 2A to 2C the leakage current voltagecharacteristic is illustrated in FIG. 2A linearly, in FIG. 2B with alogarithmic leakage current scale of its absolute amount and in FIG. 2Cwith both logarithmic scales.

For small applied bias voltages like several 10 mV a linear currentvoltage characteristic (IVC) can be observed. A quadratic dependence ofthe current from the applied voltage can be seen for moderate appliedvoltages as several 100 mV.

This IVC shape and behavior can be described as space charge limitedcurrent. Larger applied voltages result in an exponential like rise ofthe leakage current with increasing applied voltages.

The capacitor-like structure of the microelectronic device 10 shows areproducible switching behavior causing a hysteresis loop in the currentvoltage characteristic, described next below:

A large negative bias voltage-negative with respect to the SrRuO3electrode—leads to a sudden increase of the leakage current, depicted atabout −0.8 Volt. Sweeping back to large positive bias voltage theleakage current drops back to a low value again depicted at +0.7 Volt.Said sudden increase and said sudden drop back of leakage current areessential features for switching and deciding between different states.

According to the invention it is possible to operate the microelectronicdevice 10 as a very simple device or memory device, i.e. memory cell ina RAM due to and with the described underlying switching behavior. Thiswill be illustrated in conjunction with FIGS. 13A to 3C and 4A to 4C.

Basically, by applying a write voltage pulse to the microelectronicdevice 10 the system is switched into a low resistance state which canbe regarded as storing information. An erase voltage pulse recovers theresistance state of the microelectronic device 10 and the information isremoved, i.e. erased.

As can be seen in FIG. 3A a series of 300 ms long different voltagepulses depicted as sharp peaks were applied to the electrodes (12, 16)of the microelectronic device 10.

A write pulse, also called second voltage pulse 6.1, that here is anegative pulse is used to write information which after a certain delayis removed by an erase pulse, also called first voltage pulse 5.1, thathere is a positive pulse. In general, each first voltage pulse 5.1 leadsto a first state 1, a high ohmic state, and on the other hand eachsecond voltage pulse 6.1 leads to a second state 2, a low ohmic state,as can be seen from FIG. 3A in conjunction with FIG. 3C. Between therepeating voltage pulses 5.1, 6.1 a small negative read voltage 9 isswitched on and off periodically to read the information and to simulatea realistic readout process. 120 reading cycles each having a durationof 1 sec are performed after each write or erase pulse. This readoutprocedure is schematically depicted in a better time resolution by thezoomed portion in FIG. 3A.

The readout from the microelectronic device 10 is performed by measuringthe leakage current flowing at a small applied voltage of −0.2 V as itis depicted in FIG. 3B which shows current spikes occurring during writeand erase followed by the readout period with currents one order ofmagnitude lower. FIG. 3C is a leakage current scale enlargement of FIG.3B and clearly shows the above-mentioned first state 1 and second state2.

Two different resistance states can be clearly separated: The firststate 1 around 30 nano Amperes yielding a resistance of R=6.6 Mega Ohmand the second state 2 having a leakage current of 650 nano Amperesyielding a resistance of R=300 kilo Ohm. The first state 1 will now beassociated with a logic state ‘0’ and the second state 2 with a logicstate ‘1’.

The ‘1’ resistance value is 20 times smaller than the ‘0’ value. A clearseparation of the two logic states ‘1’ and ‘0’ is thus achieved.

Additionally, this remarkable dependence of the resistance on theapplied voltage pulse 5.1, 6.1 together with the hysteretic behavioralso allows to write different values to the microelectronic device 10and to read them out with a single pre-specified read-out voltage. Thisso-called multi-level switching phenomenon is discussed later in moredetail.

During the experimental measuring runs in this example information waswritten and erased during 300 ms—the duration of the sharp peaks—andstored for 240 s. The time to write and erase information was aspecifically selected experimental parameter but is not limited by thememory device itself. Therefore, the ultimate speed for the write/eraseprocess is much higher, as shown with reference to FIG. 5.

The time over which information can be stored is much longer than those240 s measured experimentally, as further measurements confirmed thatare shown in FIG. 5.

If one analyzes the switching behavior of such capacitor-like structureswith varying Cr doping it can be observed that the switching behavior ismore pronounced for slightly Cr doped structures, i.e. the best resultsare obtained with Cr-doping around 0.2% atomic percentage. For thesecapacitor-like structures the difference between ‘0’ and ‘1’ was thebest with adequate reproducibility.

Summarizing the main aspects of the present invention includes astructure having a DC-resistance changing sensitively with the appliedvoltage pulses and consisting of oxides doped can be operated as amemory device or cell with the following intriguing properties:

What is achieved is a very simple structure because the whole memorycell is a capacitor-like structure. Thus they can be operated with onlytwo terminals with a single terminal for read, write and erase. Thus,they are best adapted for ULSI technology.

Further, the difference in resistance between the ‘0’value and ‘1’ valueis at least one order of magnitude as can be seen from FIG. 3C. As canbe seen further from the IVC depicted in FIG. 2A, a large resistancerange can thus be exploited to store a plurality of different logicalvalues, i.e., the so-called multilevel switching can be achieved. Forthis, a plurality of write pulses different in size, etc., as mentionedearlier can be applied to write specific logical values into the memorycell, in order to realize not a binary system but, e.g., a digitaldecimal system based on 10 different logical values being able to bewritten into and to be read from said memory cell in subsequentwrite/read/erase cycles.

Finally, the information is stored over long times which is a remarkableadvantage compared to conventional DRAM cells.

FIGS. 4A to 4C show the operation of a further microelectronic device, asecond memory device, that can be used as a multilevel memory device.Since the FIGS. 4A to 4C are related to each other, they will beregarded in context to understand the operation of the second memorydevice. This second memory device for the sake of simplicity is notdepicted but is structured as shown in FIG. 1. The second memory devicecomprising an oxide base electrode 12 made from SrRuO3 and a region 14made from SrZrO3 slightly doped with 0.2% (atomic percentage) Chromium(Cr) for the insulating material and a metallic (Pt/Ti) top electrode 16on a SrTiO3 substrate 18 was fabricated with pulsed laser depositionagain.

As can be seen in FIG. 4A a series of different voltage pulses depictedas sharp peaks were applied to the second memory device. In particular,erase voltage pulses 5, low write pulses 6, medium write pulses 7, andhigh write pulses 8 were applied in a defined repeating sequence inorder to simulate realistic erase and write processes. Each peak of theerase voltage pulses 5 indicates 30 pulses with a duration of 1 ms. Asmall read voltage 9 were applied appropriately in intervals of 10 s inorder to read information., This read voltage 9 is smaller in magnitudethan the different voltage pulses 5, 6, 7, 8 applied for switching todifferent states 1, 2, 3, 4.

FIG. 4B shows the current generated by the different voltage pulses 5,6, 7, 8 and FIG. 4C the current readout enlargement of FIG. 4B.Different states 1, 2, 3, 4 corresponding to different ohmic resistancescan be clearly derived from FIG. 4C. The ohmic resistance of the region14 of the second memory device can be regarded as ‘high’ after one erasepulse 5 has been applied, that means that the second memory device thenstores a high ohmic state, also referred to as first state 1.Conversely, each low write pulse 6 leads to a second state 2, eachmedium write pulse 7 leads to a third state 3, and each high write pulse8 leads to a fourth state 4 whereby this fourth state 4 is the lowestohmic state. The second state 2 and the third state 3 are in-between thehigh ohmic and the lowest ohmic state. As can be seen in FIG. 4A erasepulses 5 were applied between the write pulses 6, 7, 8 to switchrespectively from the second state 2, the third state 3, or the fourthstate 4 to the first state 1.

With each of the different states 1, 2, 3, 4 a corresponding logicalvalue can be associated, e.g., the first state 1 corresponds to logical‘00’, the second state 2 corresponds to logical ‘01’, the third state 3corresponds to logical ‘10’ and the fourth state 4 corresponds tological ‘11’, representing a 2 bit memory cell. In general, more statesare possible than the depicted four different states 1, 2, 3, 4.

The erase voltage pulses 5 are here negative voltage pulses whereas thewrite pulses 6, 7, 8 are positive pulses. Basically, before a memorydevice is used the first time, an initializing voltage should be appliedto polarize this device. Depending on this polarization the erasevoltage pulses might either be positive and the write pulses negative orthe erase voltage pulses are negative and the write pulses are positive.

It shows advantageously, if each of the erase pulses 5 has an equal orsmaller magnitude of the amplitude of the write pulses 6, 7, 8.

Contrary to the example, the erase pulses 5 can have differentamplitudes for switching directly from the fourth state 4 to thedifferent states 3, 2, 1 having higher ohmic resistance. That means, inparticular, for switching from a low ohmic state, that here is thefourth state 4, to a higher ohmic state, e.g. the third state 3, thesecond state 2, or even the first state 1, the erase pulses 5 have anadapted step-like increased amplitude. Also possible in such a way is aswitching from the fourth state 4 directly to the second state 2.

The switching behavior of the multilevel memory device was investigatedand tested at 77 K, whilst the same switching behavior can be realizedat room temperature.

FIGS. 5A to 5H show results of measurements over an extended time periodon another microelectronic device, a third memory device. This thirdmemory device has the same structure as the second memory device asdescribed above with the exception that the top electrode 12 comprisesAu.

In general, within the uppermost row of figures the applied voltages aredepicted whilst in the bottom row of figures the resulting currentreadouts are shown. FIG. 5a indicates two erase pulses 5 and three writepulses 6, each of a duration of 1 ms and applied in intervals of 1 min.The current readout with the corresponding states 1, 2 are depicted inFIG. 5B. A third positive write pulses 6 on the 28.4.99 leaded to aswitch from the first state 1 to the second state 2, as can be seen fromthe figures. After that, the third memory device was stored without anypower connection and not used for a longer period of time. FIGS. 5C and5D indicate unperiodical measurements within a time period of two month,whereby the measuring dates are listed in FIG. 5D. More particular, FIG.5C indicates the read voltage pulses 9 whereas FIG. 5D depicts thecurrent readout result. The result shows that the second state 2 wasstored over a longer period of time and thus the third memory device canbe regarded as non-volatile for this time period. FIG. 5E shows furtherwrite and erase pulses, respectively, and FIG. 5F the resulting states.Finally, FIGS. 5G and 5H indicates further unperiodical measurementswithin a time period of three month, whereby the measuring dates arenamed in FIG. 5H. On one hand FIG. 5G depicts the read voltage pulses 9again whereas on the other hand FIG. 5H shows the resulting currentreadout. The measurements show again that the last information stored inthe third memory device was stored over a longer period of time withoutany decay.

With reference to FIG. 6 a schematic circuit diagram representing thearrangement of a 4-bit-memory circuit is shown.

Four microelectronic devices 10, also referred to as memory cells 10,are arranged linearly in order to represent the 4-bit-memory circuitaddressed via an address line 28 by a decoder 30 the outputs of whichare connected to a respective top electrode 16, as shown in FIG. 1. Thebase electrodes 22 thereof are each connected to ground. A write, erase,or read voltage pulse can be applied to a selected memory cell 10through a bias line 32. The different memory cells output current isevaluated through the output line 34.

In a similar way a matrix like arrangement can be achieved by connectingthe base electrodes 22 of a row of the memory cells 10 with a furtherdecoder.

It is obvious that the disclosed embodiments of the particularcomponents 12, 14, 16, 18 of the capacitor-like structure on a chip, asshown in FIG. 1, will be adapted to the requirements imposed by thespecific integration level which is intended to be achieved with thechip. A broad spectrum of different architectures can thus be realized.

Beside the capability of the memory cells 10 described above to storeinformation it is possible to use a system comprising an dopedcapacitor-like structure as an active switching element in electric orelectronic circuits.

In this area of interest a switching operation is not restricted to aspecific resistance value. Devices having a resistance of some Mega Ohmscan be operated at a voltage between 1 Volt and 5 Volt for writing anderasing and at a voltage between 0.05 Volt and 0.5 Volt for reading.Devices having a smaller resistance can also be operated, however atdifferent voltages.

Further, the present concept is suitable for an application of thesubstance for constructing EEPROMs (Electrically Easable ProgrammableRead Only Memories), logic gates as e.g. AND gates, OR-gates, tunablecapacitors and further complex logic circuits.

Particularly, when silicon (Si) or other semiconductor substrates aretaken as substrate material instead of strontium titanate the currentprior art semiconductor materials can be grown on the substrate thusproviding the ability to join conventional semiconductor technology withthe memory cells or switching elements, respectively, of the presentconcepts.

In the foregoing specification the invention has been described withreference to a specific exemplary embodiment thereof. It will, however,be evident that various modifications particularly relative to theapplication of a large variety of different substances as they arementioned in the appended claims may be made thereto without departingfrom the broader spirit and scope of the invention as set forth in theappended claims.

The specification and drawings are accordingly to be regarded asillustrative rather than in a restrictive sense.

In particular the thickness of the region 14 as well as the lateraldimensions of a memory cell and the applied bias voltages or biascurrents, respectively, can be varied as it is required by any specificpurpose imposed by any of a plurality of varying chip designs.

Also the material selection for the bottom electrode can be varied aswell. A simple metal like platinum (Pt) is suited as well.

Also for the top electrode the material can be varied as well. Au, Ptare suited materials, but principally, all metals and conducting oxidesare suited materials for both, top and bottom electrodes.

It is to be understood that the present invention is not limited to theembodiments described above, but encompasses any and all embodimentswithin the scope of the following claims:

What is claimed is:
 1. A microelectronic device for storing digitalinformation, the device having a switchable ohmic resistance betweenelectrodes, which said ohmic resistance is reversibly switchable betweendifferent states in response to application of different voltage pulsesto the electrodes, each different state corresponding to a differentvalue of stored information; wherein the ohmic resistance is formed froma substance comprising components A_(x), B_(y), and oxygen O_(z), inwhich: said component A is a member of Alkaline metals (group IA), orAlkaline Earth metals (group IIA), or Rare Earth elements, or Scandium,or Yttrium; said component B is a transition metal being member of oneof the groups IB to VIII, or a member of one of the groups IIIA, IVA,VA; and said substance comprising a dopant of one of or a combination ofdifferent transition metals, the total dopant amount in atomicpercentage being larger than 0% and smaller than 5%.
 2. Themicroelectronic device according to claim 1, wherein the ohmicresistance is switchable between at least a first state of the differentstates and a second state of the different states by applying to theelectrodes a first voltage pulse of the different voltage pulses forswitching from said second state to said first state or a second voltagepulse of the different voltage pulses for switching from said firststate to said second state.
 3. The microelectronic device according toclaim 2, wherein the ohmic resistance in the first state is higher thanin the second state and wherein the first voltage pulse of the differentvoltage pulses for switching to said first state has an opposite sign tothe second pulse of the different voltage pulses for switching to saidsecond state.
 4. The microelectronic device according to claim 1,wherein each of the different states is obtainable by an erase pulse forswitching the ohmic resistance in the region to a high ohmic state ofthe different states or by providing at least one write pulse forswitching from said high ohmic state to a lower ohmic state of thedifferent states.
 5. The microelectronic device according to claim 4,wherein the erase pulse has different amplitudes for switching to one ofthe lower ohmic states.
 6. The microelectronic device according to claim1, wherein the different states are readable by a read voltage smallerin magnitude than the different voltage pulses applied for switching tothe different states.
 7. The microelectronic device according to claim 1being usable as a capacitor-like structure, wherein the ohmic resistancerepresents a dielectric.
 8. The microelectronic device according toclaim 1, whereby a specific ohmic resistance related to one of thedifferent states remains after one of the different voltage pulses thatleads to said specific ohmic resistance has been applied to theelectrodes.
 9. The microelectronic device according to claim 1, whereinsaid stored digital information is representable by different values inohmic resistance of a region, thereby preferably storing two or morebits as digital information.
 10. The microelectronic device according toclaim 1, in which the combinations of indices x, y and z of thesubstance are definable by x=n+2, y=n+1, z=3n+4, with n=0, 1, 2, 3; orx=n+1, y=n+1, z=3n+5, with n=1, 2, 3,
 4. 11. The microelectronic deviceaccording to claim 1, in which the combinations of indices x, y and z ofthe substance are definable by either of: x=1, y=1, z=1, and one of theindices x or y being 0; or x=n, y=n, z=n+1, with n=1 or 2 and one of theindices x or y being 0; or x=n, y=n, z=2n+1, with n=2 and one of theindices x or y being
 0. 12. The microelectronic device according toclaim 1, in which the combinations of indices x, y and z of thesubstance are definable by x=n, y=n, z=3n, with n=1, or 2, or 3; orx=n+1, y=n, z=4n+1, with n=1, or
 2. 13. The microelectronic deviceaccording to claim 1, comprising a dopant of Chromium or Vanadium at anamount in atomic percentage larger than 0% and smaller than 5%.
 14. Themicroelectronic device according to claim 1, wherein at least one of thecomponents A_(x) or B_(y) of the substance comprises a combination ofelements out of one group or out of several of the corresponding groupsof A, and B, respectively.
 15. The microelectronic device according toclaim 11, wherein the substance is present in the form of a superlatticemade by a combination of structural unit cells and/or sub-unit cells.16. The microelectronic device according to claim 10, wherein thesubstance is present in the form of a superlattice made by a combinationof structural unit cells and/or sub-unit cells having each a differentn, said structural unit cells and/or sub-unit cells being each a memberof a corresponding homologous series.
 17. The microelectronic deviceaccording to claim 12, wherein the substance is present in the form of asuperlattice made by a combination of structural unit cells and/orsub-unit cells having each a different n, said structural unit cellsand/or sub-unit cells being each a member of a corresponding homologousseries.
 18. A memory cell arrangement comprising a microelectronicdevice, said microelectronic device having a switchable ohmic resistancebetween electrodes, which said ohmic resistance is reversibly switchablebetween different states in response to application of different voltagepulses to the electrodes, each different state corresponding to adifferent value of stored information; wherein the ohmic resistance isformed from a substance comprising components A_(x), B_(y), and oxygenO_(z), in which: said component A is a member of Alkaline metals (groupIA), or Alkaline Earth metals (group IIA), or Rare Earth elements, orScandium, or Yttrium; said component B is a transition metal beingmember of one of the groups IB to VIII, or a member of one of the groupsIIIA, IVA, VA; and said substance comprising a dopant of one of or acombination of different transition metals, the total dopant amount inatomic percentage being larger than 0% and smaller than 5%.
 19. Asemiconductor device comprising a microelectronic device, saidmicroelectronic device having a switchable ohmic resistance betweenelectrodes, which said ohmic resistance is reversibly switchable betweendifferent states in response to application of different voltage pulsesto the electrodes, each different state corresponding to a differentvalue of stored information; wherein the ohmic resistance is formed froma substance comprising components A_(x), B_(y), and oxygen O_(z), inwhich: said component A is a member of Alkaline metals (group IA), orAlkaline Earth metals (group IIA), or Rare Earth elements, or Scandium,or Yttrium; said component B is a transition metal being member of oneof the groups IB to VIII, or a member of one of the groups IIIA, IVA,VA; and said substance comprising a dopant of one of or a combination ofdifferent transition metals, the total dopant amount in atomicpercentage being larger than 0% and smaller than 5%.
 20. A method forwriting information into a memory cell arrangement, said memory cellarrangement comprising a microelectronic device having a switchableohmic resistance between electrodes, which said ohmic resistance isreversibly switchable between different states in response toapplication of different voltage pulses to the electrodes, eachdifferent state corresponding to a different value of storedinformation; wherein the ohmic resistance is formed from a substancecomprising components A_(x), B_(y), and oxygen O_(z), in which: saidcomponent A is a member of Alkaline metals (group IA), or Alkaline Earthmetals (group IIA), or Rare Earth elements, or Scandium, or Yttrium;said component B is a transition metal being member of one of the groupsIB to VIII, or a member of one of the groups IIIA, IVA, VA; and saidsubstance comprising a dopant of one of or a combination of differenttransition metals, the total dopant amount in atomic percentage beinglarger than 0% and smaller than 5%, wherein the method comprising thestep of: applying one voltage pulse of the different voltage pulses tothe electrodes of said memory cell arrangement for writing informationinto it.
 21. The method according to claim 20, further comprising thestep of switching the ohmic resistance in the region between at least afirst state of the different states and a second state of the differentstates by applying to the electrodes a first voltage pulse of thedifferent voltage pulses for switching from said second state to saidfirst state or a second voltage pulse of the different voltage pulsesfor switching from said first state to said second state.
 22. The methodaccording to claim 21, further comprising the step of providing an ohmicresistance in the first state higher than an ohmic resistance in thesecond state and providing the first voltage pulse for switching to saidfirst state with an opposite polarity to the second voltage pulse forswitching to said second state.
 23. The method according to claim 20,further comprising the step of obtaining each of the different states byproviding an erase pulse for switching the ohmic resistance to a highohmic state of the different states or by providing at least one writepulse for switching from said high ohmic state to a lower ohmic state ofthe different states.
 24. The method according to claim 23, furthercomprising the step of providing an erase pulse with differentamplitudes for switching to one of the lower ohmic states.
 25. A methodfor reading information out of a memory cell arrangement, said memorycell arrangement comprising a microelectronic device having a switchableohmic resistance between electrodes, which said ohmic resistance isreversibly switchable between different states in response toapplication of different voltage pulses to the electrodes, eachdifferent state corresponding to a different value of storedinformation; wherein the ohmic resistance is formed from a substancecomprising components A_(x), B_(y), and oxygen O_(z), in which: saidcomponent A is a member of Alkaline metals (group IA), or Alkaline Earthmetals (group IIA), or Rare Earth elements, or Scandium, or Yttrium;said component B is a transition metal being member of one of the groupsIB to VIII, or a member of one of the groups IIIA, IVA, VA; and saidsubstance comprising a dopant of one of or a combination of differenttransition metals, the total dopant amount in atomic percentage beinglarger than 0% and smaller than 5%, wherein the method comprising thesteps of: applying a read voltage to said memory cell arrangement andassociating with this information a value of current flowing throughsaid memory cell arrangement; or applying a current pulse to said memorycell arrangement and associating with this information a value ofvoltage appearing between the electrodes of said memory cellarrangement.
 26. Use of a substance for storing digital information, thesubstance comprising components A_(x), B_(y), and oxygen O_(z), formaking a switchable ohmic resistance within a capacitor-like structure,in which: said component A is a member of Alkaline metals (group IA), orAlkaline Earth metals (group IIA), or Rare Earth elements, or Scandium,or Yttrium, said component B is a transition metal being member of oneof the groups IB to VIII, or a member of one of the groups IIIA, IVA,VA, said substance comprises a dopant of one of or a combination ofdifferent transition metals, the total dopant amount in atomicpercentage being larger than 0% and smaller than 5%.
 27. Use of asubstance according to the claim 26, wherein the combinations of indicesx, y and z are defined by x=n+2, y=n+1, z=3n+4, with n=0, 1, 2, 3; orx=n+1, y=n+1, z=3n+5, with n=1, 2, 3, 4; or being defined by either of:x=1, y=1, z=1, and one of the indices x or y being 0, or x=n, y=n,z=n+1, with n=1 or 2 and one of the indices x or y being 0, or x=n, y=n,z=2n+1, with n=2 and one of the indices x or y being 0; or being definedby x=n, y=n, z=3n, with n=1, or 2, or 3; or x=n+1, y=n, z=4n+1, withn=1, or 2.